A new type of circuit architecture (time-interleaved double-data weighted averaging) makes efficient implementation possible in economical 130-nm standard-CMOS technology with a 1.5-V supply voltage.

At VLSI 2004 Infineon presented a high-performance 4GS/s 6bit flash ADC with 8bit output realized in a 0.13µm standard CMOS technology. The outputs of the 255 small-area comparators with ...

Test board of the multi-standard wireless transceiver Leuven, February 10, 2010 -- At today's International Solid State Circuit Conference, imec and its research partners Renesas Technology Corp. and ...

The DVB-H standard compliant SoC baseband channel decoder (S3C4F10) represents the industry’s first single-chip channel decoder solution, completed with all memories needed for Link Layer operations ...