Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by ... Stacking several decks of memory arrays (e.g. 2 decks of 64-layers to ...

A new technical paper titled “Energy-/Carbon-Aware Evaluation and Optimization of 3D IC Architecture with Digital Compute-in-Memory Designs” was published ... of increased energy efficiency compared ...