This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock domains ...

Abstract: This brief presents a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28 nm CMOS technology and uses pipelined ...

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