Figure 1 A clock-recovery circuit in an FPGA recovers data in a 1.5-Mbps data stream. The algorithm uses a 3-bit, free-running counter to generate the output clock, an 8-bit shift register to sample ...

Intelligent clock gating is key to Xilinx’s bid to reduce dynamic block-RAM (BRAM) power consumption in its Virtex-6 FPGA designs. The key to this fourth generation partial reconfiguration design flow ...