In brief Computer scientists at ETH Zurich have written a network flow algorithm that computes almost as fast as is mathematically possible. This algorithm computes the maximum traffic flow with ...

It has introduced a software tool which automatically generates HDL code from MATLAB for implementing FPGA and Asic designs from the MATLAB language. HDL Coder generates synthesisable VHDL and Verilog ...

Zahra Tajbakhsh, Parviz Fattahi, Javad Behnamian, Multi-objective assembly permutation flow shop scheduling problem: a mathematical model and a meta-heuristic algorithm, The Journal of the Operational ...